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concurrencyvhdlassert
Basil1402
Basil1402

Reputation: 21

VHDL Assert - Concurrent statements

I am trying to use VHDL assertions. In my design, I have written the assert statement directly in the DUT because I want to monitor internal signal. And since my assertion is concurrent with the instructions, the simulator raises an report almost at each input change.

I give you a minimal working example below (a simple adder). It is not my actual design, just an illustration of my problem.

How can I modify my code so that assertions are not triggered at unwanted times ? No synthesis constraints here.

Thank you in advance !

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity Full_Adder is
   port( X, Y, Cin : in std_logic;
         sum, Cout : out std_logic);
end Full_Adder;
 
architecture bhv of Full_Adder is

signal s_sum : std_logic:='0'; -- to be used in the assert
signal s_Cout : std_logic:='0'; -- to be used in the assert

begin

   s_sum <= (X xor Y) xor Cin;
   s_Cout <= (X and (Y or Cin)) or (Cin and Y);
   sum<=s_sum;
   Cout<=s_Cout;

   assert (s_sum =((X xor Y) xor Cin)) report "Erreur de somme" severity note;
   assert (s_Cout = ((X and (Y or Cin)) or (Cin and Y))) report "Erreur de retenue" severity note;

end bhv;

Testbench :

Library IEEE;
USE IEEE.Std_logic_1164.all;
entity tb_fulladder is
end tb_fulladder;
 
architecture behavioral of tb_fulladder is
 component Full_Adder
   port( 
   X, Y, Cin : in std_logic;  
  sum, Cout : out std_logic
  );  
 end component; 

 signal A,B,Cin: std_logic:='0';
 signal S,Cout: std_logic;

begin   
 structural_adder: Full_Adder port map 
   (
    X => A,
    Y => B,
    Cin => Cin,
    sum => S,
    Cout => Cout 
   );
   
process
  begin
   A <= '0';
   B <= '0';
   Cin <= '0';
   wait for 100 ns;
   A <= '0';
   B <= '0';
   Cin <= '1';
   wait for 100 ns;   
   A <= '0';
   B <= '1';
   Cin <= '0';
   wait for 100 ns;
   A <= '0';
   B <= '1';
   Cin <= '1';
   wait for 100 ns;
   A <= '1';
   B <= '0';
   Cin <= '0';
   wait for 100 ns;
   A <= '1';
   B <= '0';
   Cin <= '1';
   wait for 100 ns;
   A <= '1';
   B <= '1';
   Cin <= '0';
   wait for 100 ns;   
   A <= '1';
   B <= '1';
   Cin <= '1';
   wait for 100 ns;   
  end process;
      
end behavioral;

Upvotes: 0

Views: 651

Answers (1)

Nurullah &#199;.
Nurullah &#199;.

Reputation: 1

You can code your assertions in a process structure that its sensitivity list can be used for control signals like followings;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity Full_Adder is
   port( X, Y, Cin : in std_logic;
         sum, Cout : out std_logic);
end Full_Adder;
 
architecture bhv of Full_Adder is

signal s_sum : std_logic:='0'; -- to be used in the assert
signal s_Cout : std_logic:='0'; -- to be used in the assert

begin

   s_sum <= (X xor Y) xor Cin;
   s_Cout <= (X and (Y or Cin)) or (Cin and Y);
   sum<=s_sum;
   Cout<=s_Cout;

   process(<related signals>) begin
      assert (s_sum =((X xor Y) xor Cin)) report "Erreur de somme" severity note;
      assert (s_Cout = ((X and (Y or Cin)) or (Cin and Y))) report "Erreur de retenue" severity note;
   end process;

end bhv;

By the way, you can use the same piece of code in testbench, but you may not receive internal design signals this way.

Good luck.

Upvotes: 0

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