CODEWITHSUNDEEP
verilog
eliesmith
eliesmith

Reputation: 59

Verilog Testbench module not found

I am trying to make my first program testbench and having an error calle " error: Unknown module type: circuit 2 error(s) during elaboration.

*** These modules were missing:
        circuit referenced 1 times.
***".

Can someone please help me with this? I tried different ways of calling the module. Here is the code:

module circuit (a,b,c,d,o);
input a,b,c,d;
output o;
wire e,f,g,h,i,j,k,l,m,n;
not (e,a);
not (f,b);
not (g,c);
not (h,d);
and (I,e,g);
and (j,e,f,c,h);
and (k,a,f,g,h);
and (l,a,c);
and (m,b,g,d);
and (n,b,c,d);
or (o,i);
or (o,j);
or (o,k);
or (o,l);
or (o,m);
or (o,n);

endmodule

And here is the testbench code

module TB_circuit;  
reg a1,b1,c1,d1;
wire o1;
circuit my_module(a1,b1,c1,d1,o1);
initial
begin
a1=0;
c1=0;
#period;
end
endmodule

Both are different file but in same folder. Any help would be appreciated. Thanks!

Upvotes: 0

Views: 3319

Answers (1)

toolic
toolic

Reputation: 62163

You need to declare period as a parameter and set it to a numeric value, such as 50:

module TB_circuit;  
    reg a1,b1,c1,d1;
    wire o1;
    parameter period = 50;
    circuit my_module(a1,b1,c1,d1,o1);
initial
begin
    a1=0;
    c1=0;
    #period;
end
endmodule

Here is an example on edaplayground which compiles. It is free, but you do need to sign up for an account.

Upvotes: 0

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