CODEWITHSUNDEEP
logicverilogsystem-verilog
user16818402
user16818402

Reputation: 9

Different instances of a System Verilog Module have different behaviour

always @ (RSTDAC_B or EN or  DSR or  DSR_B )
        begin
            if (RSTDAC_B === 1'b0) begin stepp = 1'b0; stepn = 1'b0; end
       else if (RSTDAC_B === 1'b1) begin    
                 if (EN & DSR   === 1'b1)  begin stepn = 1'b1;end
             else if (EN & DSR_B  === 1'b1) begin stepp = 1'b1;end
                                    end
        end

The code above is from a Dynamic Register Module instantiated 8 times in the design. The intention is that when EN(able) is high then either stepp or stepn is high depending on if DSR or DSR_B is high. I am seeing that when DSR_B goes high, stepp and stepn BOTH go high in 6 out of 8 instances. In 2 instances, the design behaves as intended and only stepp goes high when EN & DSR_B are high.

I have seen this happen on multiple tools so I don't think its the tool's fault. Thanks

Upvotes: 0

Views: 61

Answers (1)

dave_59
dave_59

Reputation: 42623

This is not valid combinational logic. You must make assignments to all variables in all possible branches of your code. You are not doing that with stepn and stepp

If you are using SystemVerilog, you should be using always_comb instead of always @(explicit_list_of_signals)

Upvotes: 1

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