CODEWITHSUNDEEP
verilogxilinxhdlintel-fpgaxilinx-ise
Arslan Majid
Arslan Majid

Reputation: 49

Synthesis error of Array Multiplication with an input

Hello I am trying a small section of a project code where the equation is multiplying input with all values of array and then adding them up in one final output.

module arraywithinput(input in,
    output reg [11:0] out0
    );

reg [7:0] xin[3:0];


initial 
begin
xin[0]=7;
xin[1]=6;
xin[2]=5;
xin[3]=2;
end



integer i;

always@(*)
begin
for (i=0; i<4; i=i+1)
out0<=out0+(in*xin[i]);
end

endmodule

I am getting synthesis error of Unexpected xin event in always block sensitivity list. What could I be possibly doing wrong to implement this scenario.

Upvotes: -1

Views: 85

Answers (1)

Pradyuman Bissa
Pradyuman Bissa

Reputation: 191

Initial blocks are not synthesizable constructs and are intended for test benches only. Also it is not advisable to have NBA in an always@* block. Mult/Div are compute intense and use lot of resources, better to use some algorithm like repeated addition, booth etc to implement multipication.

I have modified your code. I have used a clock signal.

module arraywithinput(input in,
                      input clk,
                      output [11:0] out0
                );

 reg [7:0]xin[3:0];
 reg [11:0] out0_r[3:0];

 always@(*)  
 begin 
  xin[0]=7; 
  xin[1]=6;
  xin[2]=5;
  xin[3]=2;
 end

 integer i;

 always@(posedge clk)
 begin
   out0_r[0] <= (in*xin[0]);
  for (i=1; i<4; i=i+1)
   out0_r[i] <= out0_r[i-1] + (in*xin[i]);
 end

 assign out0 = out0_w[3];  //Please note that output will be stable after 4 cycles.
 
endmodule

Upvotes: -1

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