CODEWITHSUNDEEP
verilogsystem-verilogfpga
asimtot
asimtot

Reputation: 185

How to get rid of the error <variableName> is not constant while trying to do simple number comparison?

I am new to SystemVerilog and Basys3. I am trying to learn seven segment display. To do that, I wrote a simple demo which will do:

1- Take input from switches
2- From that Input, decide which seven segment output will be used with comparing numbers
3- Display on the seven segment display.

You can see my code.

module SevenSegmentNumber(input logic[3:0] inputFile, output logic [6:0] outputFile);
    
    if (inputFile == 3'b000) begin
        assign outputFile[6] = 0;
        assign outputFile[5] = 0;
        assign outputFile[4] = 0;
        assign outputFile[3] = 0;
        assign outputFile[2] = 0;
        assign outputFile[1] = 0;
        assign outputFile[0] = 1;
    end
    
    else if (inputFile == 3'b001) begin
            assign outputFile[6] = 1;
            assign outputFile[5] = 0;
            assign outputFile[4] = 0;
            assign outputFile[3] = 1;
            assign outputFile[2] = 1;
            assign outputFile[1] = 1;
            assign outputFile[0] = 1;
    end
    
    else if (inputFile == 3'b010) begin
            assign outputFile[6] = 0;
            assign outputFile[5] = 0;
            assign outputFile[4] = 1;
            assign outputFile[3] = 0;
            assign outputFile[2] = 0;
            assign outputFile[1] = 1;
            assign outputFile[0] = 0;
    end
endmodule

assign outputFile[n] is hardcoded according to how seven segment display is work which I found on the Internet.

My problem here is I cannot compare whether input file is equal 0 or 1 or 2

Error message is:

inputFile is not constant

I also tried to code with form

inputFile == 0
inputFile == 1
inputFile == 2

Which did not solve my problems. How can I solve this problem?

Upvotes: 1

Views: 124

Answers (1)

toolic
toolic

Reputation: 62236

Your error message informs you that the inputFile input port can not be used in that way because it is a variable type. Your code looks like it is using an implicit generate construct, which requires inputFile to be a constant type, such as a parameter.

One way to fix your code is to place your if/else statement inside a procedural block. Since you are describing combinational logic, you can use always_comb. In this case, there is no need to use the assign keyword.

module SevenSegmentNumber(input logic[3:0] inputFile, output logic [6:0] outputFile);
    
always_comb begin
    outputFile = '0;

    if (inputFile == 3'b000) begin
        outputFile[6] = 0;
        outputFile[5] = 0;
        outputFile[4] = 0;
        outputFile[3] = 0;
        outputFile[2] = 0;
        outputFile[1] = 0;
        outputFile[0] = 1;
    end
    
    else if (inputFile == 3'b001) begin
        outputFile[6] = 1;
        outputFile[5] = 0;
        outputFile[4] = 0;
        outputFile[3] = 1;
        outputFile[2] = 1;
        outputFile[1] = 1;
        outputFile[0] = 1;
    end
    
    else if (inputFile == 3'b010) begin
        outputFile[6] = 0;
        outputFile[5] = 0;
        outputFile[4] = 1;
        outputFile[3] = 0;
        outputFile[2] = 0;
        outputFile[1] = 1;
        outputFile[0] = 0;
    end
end

endmodule

Note that I initialized outputFile to 0 at the top of the block. This avoids inferring latches when synthesized. You can change 0 to be something more meaningful to your design (whatever your logic should do when the input is not 0, 1 or 2).

Upvotes: 1

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