CODEWITHSUNDEEP
verilogvivadoiverilog
Celuk
Celuk

Reputation: 897

iverilog Not Compiling Multiple Port Declarations With Multiple Bits Written In One Line

I am trying to compile Verilog code with a testbench with the last stable version of iverilog 11.0; here is an example:

iverilog -o example example.v tb_example.v

// example.v

module example(
    input [1:0] input1, [1:0] input2, // problem is here
    output [1:0] output1
    );

// ...

endmodule

// tb_example.v

module tb_example(

    );

    reg [1:0] input1;
    reg [1:0] input2;
    wire [1:0] output1;
    
    example uut(input1, input2, output1);

// ...

endmodule

Although there is no problem compiling in Vivado, the code above cannot be compiled by iverilog and gives this syntax error:

example.v:2: syntax error
example.v:1: Errors in port declarations.

When I changed the input declaration line in example.v to this:

input [1:0] input1, input2, // still one line but second bit declaration removed

or to this:

input [1:0] input1, 
input [1:0] input2, // seperate lines

there is no problem, and it can be compiled by iverilog without errors.

So, if the problem is over, why I am asking this? Because firstly, I don't understand that this can be compiling in vivado and not in iverilog, and secondly, I need to control multiple files written like this (written multiple ports with multiple bits in one line) with testbenches, and it is hard to change all of them.

Am I missing something, or does iverilog not support this?

Upvotes: 2

Views: 948

Answers (1)

dave_59
dave_59

Reputation: 42788

This is legal in Verilog, but appears to be a bug with . It's not whether you write it on separate lines, but iverilog wants a port direction before any type declaration. So you have to use one of your workarounds or the following:

input [1:0] input1, input [1:0] input2,

Upvotes: 3

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