CODEWITHSUNDEEP
vhdl
user19021241
user19021241

Reputation: 13

What is this VHDL 10309 error code all about?

I'm running with 2 projects right now and I have problems with same topics to be fixed - VHDL Interface Declaration error known as ID 10309(Interface object of mode out cannot be read. Change object mode to buffer).

So the first one is about Sorting Circuit that compares which is large and which is not for 2 variables - and needs to be 7-segmented for each of them.

library ieee;
use ieee.std_logic_1164.all;

package use_package is 
 constant sorting_in_width : integer :=4;
 constant sorting_out_width : integer :=4;
 subtype sorting_in_value is integer range 0 to 2**sorting_in_width-1;
 subtype sorting_out_value is integer range 0 to 2**sorting_out_width-1;
end use_package;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.use_package.all;

entity SortingCircuit is 
 port (  a, b     : in  sorting_in_value;
    enable   : in std_logic;
    min, max : out sorting_out_value);
end SortingCircuit;

architecture SC_Design of SortingCircuit is 
signal maxSeg, minSeg : integer range 0 to 15; 
  begin
   process(a,b)
     begin
     if (enable = '1') then 
     if (a>b) then
       max <= a;
      min <= b;
     case maxSeg is
        when 0 => max <= "1111110";
        when 1 => max <= "0110000";
        when 2 => max <= "1101101";
        when 3 => max <= "1111001";
        when 4 => max <= "0111011";
        when 5 => max <= "1011011";
        when 6 => max <= "1011111";
        when 7 => max <= "1110000";
        when 8 => max <= "1111111";
        when 9 => max <= "1111011";
        when 10 => max <= "1111101";
        when 11 => max <= "0011111";
        when 12 => max <= "0001101";
        when 13 => max <= "0111101";
        when 14 => max <= "1101111";
        when 15 => max <= "1000111";
      end case;
      case minSeg is
        when 0 => b <= "1111110";
        when 1 => b <= "0110000";
        when 2 => b <= "1101101";
        when 3 => b <= "1111001";
        when 4 => b <= "0111011";
        when 5 => b <= "1011011";
        when 6 => b <= "1011111";
        when 7 => b <= "1110000";
        when 8 => b <= "1111111";
        when 9 => b <= "1111011";
        when 10 => b <= "1111101";
        when 11 => b <= "0011111";
        when 12 => b <= "0001101";
        when 13 => b <= "0111101";
        when 14 => b <= "1101111";
        when 15 => b <= "1000111";
      end case;
      else
       max<= b;
       min<= a;
    case maxSeg is
        when 0 => b <= "1111110";
        when 1 => b <= "0110000";
        when 2 => b <= "1101101";
        when 3 => b <= "1111001";
        when 4 => b <= "0111011";
        when 5 => b <= "1011011";
        when 6 => b <= "1011111";
        when 7 => b <= "1110000";
        when 8 => b <= "1111111";
        when 9 => b <= "1111011";
        when 10 => b <= "1111101";
        when 11 => b <= "0011111";
        when 12 => b <= "0001101";
        when 13 => b <= "0111101";
        when 14 => b <= "1101111";
        when 15 => b <= "1000111";
      end case; 
      case minSeg is
        when 0 => a <= "1111110";
        when 1 => a <= "0110000";
        when 2 => a <= "1101101";
        when 3 => a <= "1111001";
        when 4 => a <= "0111011";
        when 5 => a <= "1011011";
        when 6 => a <= "1011111";
        when 7 => a <= "1110000";
        when 8 => a <= "1111111";
        when 9 => a <= "1111011";
        when 10 => a <= "1111101";
        when 11 => a <= "0011111";
        when 12 => a <= "0001101";
        when 13 => a <= "0111101";
        when 14 => a <= "1101111";
        when 15 => a <= "1000111";
      end case;
      end if;
    end if;
 end process;
end SC_Design;

As you could know by C-Ping it and run it, you will notice that max is not adequate for the 7-segment code. The same goes another code - which is a BCD Adder, of course needs to be 7-segmented - has the same topic.

library ieee;
use ieee.std_logic_1164.all;
package use_package is
 constant add_width : integer := 4;
 constant result_width: integer :=4;
 subtype add_value is integer range 0 to 2**add_width-1;
 subtype result_value is integer range 0 to 2**result_width-1;
end use_package;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.use_package.all;

entity BCDAdder is
    port(  a,b  : in  add_value; --in integers
          mid_sum_out : out result_value;
        seg1  : out std_logic_vector(7 downto 0); 
        seg2 : out std_logic_vector(7 downto 0));
end BCDAdder;

architecture arch of BCDAdder is
begin
 process(a,b)
 variable carry : integer; --middle integer for carry, will be 7-segmentated after calculated
 begin
    mid_sum_out <= 0;
    mid_sum_out <= a + b; -- possible mid_sum, like 0A or so
    if(mid_sum_out > 9) then --!error point!
        seg1 <= "0110000"; --changes into 7-segmentated digits
        carry <= resize((mid_sum_out - 9),1); 
    else
        seg1 <= "1111110";
        carry <= mid_sum_out;
    end if; 
     case carry is
        when 0 => seg2 <= "1111110";
        when 1 => seg2 <= "0110000";
        when 2 => seg2 <= "1101101";
        when 3 => seg2 <= "1111001";
        when 4 => seg2 <= "0111011";
        when 5 => seg2 <= "1011011";
        when 6 => seg2 <= "1011111";
        when 7 => seg2 <= "1110000";
        when 8 => seg2 <= "1111111";
        when 9 => seg2 <= "1111011";
        when 10 => seg2 <= "1111101";
        when 11 => seg2 <= "0011111";
        when 12 => seg2 <= "0001101";
        when 13 => seg2 <= "0111101";
        when 14 => seg2 <= "1101111";
        when 15 => seg2 <= "1000111";
  end case;       
 end process;   
end arch;

At least I remember that modern programming tools like C, python, and Java have permission to allow the latter variables do their jobs either change to another form, or work as a variable in a function.

What does this error mean? And, how should I fix this?

Upvotes: 1

Views: 597

Answers (1)

Tricky
Tricky

Reputation: 4461

Interface object of mode out cannot be read: In VHDL versions prior to VHDL 2008, ports of mode out could not be read inside the code. You have an example here: carry <= mid_sum_out; where mid_sum_out is an out port of the entity.

The answers to this are:

  1. Change compile vhdl version to VHDL 2008
  2. Use an intermediate internal signal eg:
signal mid_sum_out_i : result_value;

...
mid_sum_out_i <= a + b;
carry <= mid_sum_out_i;

... outside process

mid_sum_out <= mid_sum_out_i;
  1. Change mode out to mode buffer (I recommend you dont do this)

Upvotes: 1

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