CODEWITHSUNDEEP
verilogsystem-verilog
Yike Wang
Yike Wang

Reputation: 23

Why can‘t I use wildcards in the "if" in the conditional statement？

Why does this code display no and no1?

bit[2:0] a;
a=3'b001;
if(a==3'b0??) $display("ok");
else          $display("no");

case(a)
  3'b0?? : $display("ok1");
  default: $display("no1");
endcase

I am using VCS. I don't know why the printed result is not expected.

Upvotes: 1

Views: 199

Answers (1)

Matthew
Matthew

Reputation: 13987

In (System)Verilog ? is an exact synonym for z. It is NOT a wildcard. However, it can be used as a wildcard in some situations, but not your situations. Here are those situations:

if(a ==? 3'b0??) $display("ok");
//   ^^^
else           $display("no");

casez(a)
//  ^
  3'b0??: $display("ok1");
  default: $display("no1");
endcase

case (a) inside
//       ^^^^^^
  3'b0??: $display("ok1");
  default: $display("no1");
endcase

I would use case ... inside rather than casez, because casez is an inferior, Verilog way of doing it.

Upvotes: 3

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