CODEWITHSUNDEEP
verilogsystem-verilog
Prashant Saxena
Prashant Saxena

Reputation: 19

Wildcard operator in system verilog and its synthesizability

what are Wildcard operators in system verilog? I have searched the net but there is some ambiguity.

Also are they synthesizable?

Answers for below?

4'b1010 ==? 4'b10x0 
4'b10x0 ==? 4'b1010

Upvotes: 0

Views: 2232

Answers (2)

Mac
Mac

Reputation: 357

From section 5.5 of "IEEE Standard for Verilog Register Transfer Level Synthesis" IEEE Std 1364.1-2002 (1364 is the base specification that IEEE-1800 extended, and 1361.1 defined the synthesizable subset of 1364):

The value x may be used in case item expressions (may be mixed 
with other expressions, such as 4'b01x0) in a casex statement to 
imply a don't care value for synthesis.

As the Wildcard operator is an obvious extension of the casex expression, one would reasonably expect that it is intended to be synthesizable. I am not aware of an IEEE standard for 1800 that defines the synthesizable subset; or if this information is contained in the IEEE-1800 standard itself.

The late Stuart Sutherland proposed a list of synthesizable constructs for IEEE-1800 which included the Wildcard Equality, in his paper: https://sutherland-hdl.com/papers/2006-DVCon_SystemVerilog_synthesis_subset_paper.pdf

As a matter of practicality, the definitive way to check such a question is code up a small example using this construct, and feed it to the synthesis tool you are actually planning to use and see if you get warnings, errors, or working code!

Upvotes: 0

dave_59
dave_59

Reputation: 42673

It looks like you didn't search the IEEE 1800-2017 SystemVerilog LRM. Section 11.4.6 Wildcard equality operators defines this operator. A search would give many other examples like here.

Wildcard equality operators are intended to be synthesizable as long as the X appears on the RHS as a literal or constant expression. X's on the RHS are treated as don't care matches. X's on the LHS do not match anything and only used in simulation. The inside operator and the case inside conditional statement all use this asymmetric wildcard matching for synthesizable don't cares.

Upvotes: 1

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