With Chisel How to avoid verilog file list at the end of generated file when using BlackBox?

Question

I'm using Blackbox with setInLine function in a design.

class ResetGenEna(delayClk: Int) extends BlackBox with HasBlackBoxInline {
  val io = IO(new Bundle {
    val clk = Input(Clock())
    val ena = Input(Bool())
    val rst = Output(Bool())
  })

  val cptWidth = log2Ceil(delayClk)
  val cptMsb = cptWidth - 1
  setInline("ResetGenEna.v",
    f"""
    |module ResetGenEna(
    |    input clk,
    |    input ena,
    |    output rst
    |);
    |
    |reg reset_reg = 0;
    |reg [$cptMsb%d:0] reset_dly_cnt = 0;
    |always@(posedge clk, negedge ena) begin
    |  if(!ena)
    |  begin
    |    reset_dly_cnt <= $cptWidth%d'd0;
    |    reset_reg <= 0;
    |  end
    |  else
    |  begin
    |    if(reset_dly_cnt < $cptWidth%d'd$delayClk%d)
    |      reset_dly_cnt <= reset_dly_cnt + 1'b1;
    |    else
    |      reset_reg <= 1;
    |  end
    |end
    |
    |assign rst = !reset_reg;
    |endmodule
    """.stripMargin)
}

When I generate verilog, the filename is printed at the end of file :

class SNesPadLed(val mainClockFreq: Int = 100,
                 val clockFreq: Int = 1) extends RawModule {
//...
  val rstgen = Module(new ResetGen())
//...
//...
}

object SNesPadLed extends App {
  println("Generating snespadled verilog")
  val verilog_src = ChiselStage.emitSystemVerilogFile(
      new SNesPadLed(),
      firtoolOpts = Array("-disable-all-randomization",
                          "-strip-debug-info"))
}

At the end of generated file SNesPadLed.sv I got :

//...
// ----- 8< ----- FILE "./ResetGenEna.v" ----- 8< -----


module ResetGenEna(
    input clk,
    input ena,
    output rst
);

reg reset_reg = 0;
reg [7:0] reset_dly_cnt = 0;
always@(posedge clk, negedge ena) begin
  if(!ena)
  begin
    reset_dly_cnt <= 8'd0;
    reset_reg <= 0;
  end
  else
  begin
    if(reset_dly_cnt < 8'd255)
      reset_dly_cnt <= reset_dly_cnt + 1'b1;
    else
      reset_reg <= 1;
  end
end
 
assign rst = !reset_reg;
endmodule
    

// ----- 8< ----- FILE "firrtl_black_box_resource_files.f" ----- 8< -----

ResetGenEna.v

Is it possible to avoid the name ResetGenEna.v to be printed at the end ?

I'm using chisel version 6.2.0.