Chisel3 VCD waveform dump does not update a signal

Question

I am simulating a simple AND gate in Chisel3/Scala.

import chisel3._

class ChiselPractice extends Module {
  val io = IO(new Bundle {
    val in1 = Input(Bool())
    val in2 = Input(Bool())
    val out = Output(Bool())
  })

  io.out := io.in1 & io.in2
}

Here is the testbench

import chiseltest._
import org.scalatest.freespec.AnyFreeSpec
import chisel3._

class ChiselPracticeTest extends AnyFreeSpec with ChiselScalatestTester {
  "Fork and Join"  in {
    test(new ChiselPractice).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
      fork {
        println("Task 1: Starting")
        dut.io.in1.poke(true.B)
        println(s"Task 1: in1 = ${dut.io.in1.peek().litValue}") // Debug print
        dut.clock.step(5)
        dut.io.in1.poke(false.B)
        println(s"Task 1: in1 updated to = ${dut.io.in1.peek().litValue}") // Debug print
      }.fork {
        println("Task 2: Starting")
        dut.io.in2.poke(false.B)
        println(s"Task 2: in2 = ${dut.io.in2.peek().litValue}") // Debug print
        dut.clock.step(2)
        dut.io.in2.poke(true.B)
        println(s"Task 2: in2 updated to = ${dut.io.in2.peek().litValue}") // Debug print
      }.join() // Wait for both tasks to complete

      // Final check with a print statement
      println(s"Final output (out) = ${dut.io.out.peek().litValue}")
      dut.io.out.expect(false.B) // Check that the output is correct
    }
  }
}

println statements in the testench print the values of in2 correctly however VCD dump does not show in2 updating to 1.

Task 1: Starting
Task 1: in1 = 1
Task 2: Starting
Task 2: in2 = 0
Task 2: in2 updated to = 1
Task 1: in1 updated to = 0
Final output (out) = 0