CODEWITHSUNDEEP
vhdl
Caleb Jares
Caleb Jares

Reputation: 6307

How to test a VHDL file

I've made a dual port register bank in VHDL, and I want to test it to make sure it works. How would I go about doing this? I know what I want to do (set register 2 to be a constant, read out of it in test program, write to register 3 and read it back out and see if I have the same results).

Only thing is, I'm new to VHDL, so I don't know if there's a console or how a test program is structured or how to instantiate the register file, or even what to compile it in (I've been using quartus so far).

Here's my register file:

use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

-- Register File

entity RF is

port(
    signal clk, we: in std_logic;
    signal ImmediateValue : in std_logic_vector(15 downto 0);
    signal RegisterSelectA, RegisterSelectB : in integer range 0 to 15;

    signal AOut, BOut : out std_logic_vector(15 downto 0)
);

end RF

architecture behavior of RF is

    array std_logic_vector_field is array(15 downto 0) of std_logic_vector(15 downto 0);
    variable registers : std_logic_vector(15 downto 0);

    process (clk, we, RegisterSelectA, RegisterSelectB, ImmediateValue)
        wait until clk'event and clk = '1';
        registers(RegisterSelectA) := ImmediateValue when we = '1';
        AOut <= registers(RegisterSelectA);
        BOut <= registers(RegisterSelectB);
    end process;

end behavior;

Upvotes: 0

Views: 2100

Answers (1)

wjl
wjl

Reputation: 7765

First of all, if you are new to VHDL design, you might be best off starting with a tutorial on the web, or grabbing a book like "The Designer's Guide to VHDL".

Anyway, just like a software design, to test a VHDL design, you have to write some test code. In hardware design, usually these tests are unit-test like, but are often called "testbenches".

For the design you've given, you'll need to create something like this:

library ieee.std_logic_1164.all;
library ieee.numeric_std.all;

entity test_RF is
end entity;

architecture test of test_RF is
  signal clk, we: std_logic;
  signal ImmediateValue : std_logic_vector(15 downto 0);
  signal RegisterSelectA, RegisterSelectB : integer range 0 to 15;
  signal AOut, BOut : std_logic_vector(15 downto 0)
begin

  -- Instantiate the design under test
  u_RF : entity work.RF
  port map (
    clk => clk,
    we  => we,
    ImmediateValue => ImmediateValue,
    RegisterSelectA => RegisterSelectA,
    RegisterSelectB => RegisterSelectB,
    AOut => AOut,
    BOut => BOut
  );

  -- create a clock
  process is
  begin
    clk <= '0';
    loop
      wait for 10 ns;
      clk <= not clk;
    end loop;
  end process;

  -- create one or more processes to drive the inputs and read the outputs
  process is
  begin
    wait until rising_edge(clk);
    -- do stuff
    -- use assert to check things
    -- etc
  end process;

end architecture;

Upvotes: 6

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