FF/Latch and other warnings

Question

What is wrong with my VHDL code? Here is the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    port(
        -- 50 MHz clock
        cp : in std_logic;
        -- Reset signal
        reset : in std_logic;
        -- PS/2 data and clock lines
        ps2d, ps2c : in std_logic;
        -- 7-segment display segments
        segments : out std_logic_vector (7 downto 0);
        -- Anode control
        an : out std_logic_vector (3 downto 0);
        -- Data out to LEDs
        dout : out std_logic_vector (7 downto 0)
    );
end main;

architecture Behavioral of main is
    -- Data from keyboard entity (scancode)
    signal data : std_logic_vector (7 downto 0);
    -- 7 segments of display
    signal segReg, segNext : std_logic_vector (6 downto 0);
    signal tickDone : std_logic;
begin
    -- Just an entity that reads PS/2 keyboard data
    -- rx_done is tick (20 ns)
    S1: entity keyboard port map ( cp => cp, ps2d => ps2d, ps2c => ps2c,
                          rx_done => tickDone, dout => data);
    dout <= data;
    an <= "1110";
    segments(6 downto 0) <= segReg;
    -- Turn off dot
    segments(7) <= '1';
    process (cp, reset)
    begin
        if reset = '1' then
            segReg <= (others => '0');
        elsif rising_edge (cp) then
            segReg <= segNext;
        end if;
    end process;

    process (tickDone, segReg)
    begin
        segNext <= segReg;
        if tickDone = '1' then
            if data = x"16" then
                -- Number 1
                segNext <= "1001111";
            elsif data = x"1E" then
                -- Number 2
                segNext <= "0010010";
            elsif data = x"26" then
                -- Number 3
                segNext <= "0000110";
            elsif data = x"25" then
                -- Number 4
                segNext <= "1001100";
            else
                segNext <= "1111111";
            end if;
        end if;
    end process;

end Behavioral;

When I try to synthesize it/generate programming file, I get these warnings:

WARNING:Xst:819 - "C:/VHDL_projekti/PS2K/main.vhd" line 48: The following signals are missing in the process sensitivity list:
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:1710 - FF/Latch  <segReg_0> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_1> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_2> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_3> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_4> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_5> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1710 - FF/Latch  <segReg_0> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_1> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_2> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_3> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_4> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <segReg_5> (without init value) has a constant value of 0 in block <main>.
WARNING:Par:288 - The signal reset_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:PhysDesignRules:367 - The signal <reset_IBUF> is incomplete. The signal

I've been looking at the code and I don't see anything wrong, but obviously I'm doing something wrong.

1. "The following signals are missing in the process sensitivity list" Is this maybe Xilinx ISE bug? I don't see why I would need any other signals in process sensitivity list on line 48...

2. "Due to other FF/Latch trimming, has a constant value of 0 in block" OK, what am I doing wrong? I don't want to use latches at all ...

3. "The signal reset_IBUF has no load. PAR will not attempt to route this signal. " What does this mean? What is wrong with my reset signal? Why is it incomplete?

This code is my attempt at using a PS/2 keyboard with Spartan-3 starter board. The entity "keyboard" does the reading, and it is working properly (when I test it alone, I get correct scan codes on the dout signal (I see it on LEDs)). rx_done is tick (20 ns) that signals that scancode has been successfully read.

So I just wanted to see if I can somehow recognize the scan codes (in my second process I'm comparing data signal and putting right values to segNext signal) and display something on the seven-segment display. When I get this to work, I'll then implement correct behaviour (detecting all scan codes, for extra keys and for key down and key up events).

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    port(
        -- 50 MHz clock
        cp : in std_logic;
        -- Reset signal
        reset : in std_logic;
        -- PS/2 data and clock lines
        ps2d, ps2c : in std_logic;
        -- 7-segment display segments
        segments : out std_logic_vector (7 downto 0);
        -- Anode control
        an : out std_logic_vector (3 downto 0);
        -- Data out to LEDs
        dout : out std_logic_vector (7 downto 0)
    );
end main;

architecture Behavioral of main is
    -- Data from keyboard entity (scancode)
    signal data : std_logic_vector (7 downto 0);
    -- 7 segments of display
    signal segReg, segNext : std_logic_vector (6 downto 0);
    signal tickDone : std_logic;
begin
    -- Just entity that reads PS/2 keyboard data
    -- rx_done is tick (20 ns)
    S1: entity keyboard port map ( cp => cp, ps2d => ps2d, ps2c => ps2c,
                          rx_done => tickDone, dout => data);
    dout <= data;
    an <= "1110";
    segments(6 downto 0) <= segReg;
    -- Turn off dot
    segments(7) <= '1';
    process (cp, reset)
    begin
        if reset = '1' then
            segReg <= (others => '0');
        elsif rising_edge (cp) then
            segReg <= segNext;
        end if;
    end process;

    process (tickDone, segReg, data)
    begin
        if tickDone = '1' then
            if data = x"16" then
                -- Number 1
                segNext <= "1001111";
            elsif data = x"1E" then
                -- Number 2
                segNext <= "0010010";
            elsif data = x"26" then
                -- Number 3
                segNext <= "0000110";
            elsif data = x"25" then
                -- Number 4
                segNext <= "1001100";
            else
                segNext <= "1111111";
            end if;
        else
            segNext <= segReg;
        end if;
    end process;

end Behavioral;

Unfortunately, after these edits, I still have this warnings:

WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_6> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Par:288 - The signal reset_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Answer 1

2) "Due to other FF/Latch trimming, has a constant value of 0 in block" OK, what am I doing wrong ? I don't want to use latches at all ...

This is telling you these storage elements are driven by constants, not that they are latches. Have you simulated this?

Answer 2

In your combinational process, you are reading tickDone, segReg and data. The latter is missing from your sensitivity list, which causes a latch.

Also, don't use STD_LOGIC_ARITH or STD_LOGIC_UNSIGNED. They are not standardized and have several problems. http://parallelpoints.com/node/3

Answer 3

Your second process appears to be attempting to use tickDone as a clock signal, but you are not using it appropriately (ie: if rising_edge(tickDone) or similar) so you are creating latches instead of flip-flops (if tickDone='1'). With your latches, while tickDone is high, the outputs depend on the state of the data signal, which is not in your sensitivity list. Finally, with segReg in your sensitivity list, the way the code is written, you are making an asynchronous assignment of segReg to segNext.

Did you perhaps forget to wrap everything in the second process in an if statement using the cp signal as a clock? What you've written would make a lot more sense that way...