StackOverflow Questions for Tag: axi4

xlgforever

Reputation: 23

using rocket chip(a library of chisel) to generate a axi4crossbar in verilog language

chiselrocket-chipaxi4

Score: 1

Answers: 1

PhilMasteG

Reputation: 3185

Is there a way to synchronize custom interrupt signals with AXI master transactions in Vitis HLS?

interruptxilinxvivadozynqaxi4

Score: 4

Answers: 1

Zhibo Shen

Reputation: 145

How can AXI4 support PCIE Producer/Consumer ordering model?

pci-eaxi4

Score: 0

Answers: 1

CJC

Reputation: 817

Xilinx, Zynq, AXI4 interconnect. What are the performance implications of configuring register slice and data fifo options?

xilinxvivadozynqaxi4

Score: 3

Answers: 1

CJC

Reputation: 817

AXI Protocol, difference between secure and non-secure transactions

vivadozynqaxi4

Score: 5

Answers: 1

CJC

Reputation: 817

Vivado, Zynq, BRAM Controller, Narrow AXI burst option

xilinxvivadozynqaxi4

Score: 5

Answers: 1

sheridp

Reputation: 1396

AXI4-Stream Position Bytes

ambaaxi4axi4-stream

Score: 4

Answers: 1

MateoConLechuga

Reputation: 562

MicroBlaze AXI4 Exceptions

embeddedmicroblazeaxi4

Score: 1

Answers: 1

MateoConLechuga

Reputation: 562

AXI4 AxVALID high in same clock

axi4

Score: 0

Answers: 1

MateoConLechuga

Reputation: 562

AXI4 delay transactions

vhdlhdlvlsiaxi4

Score: 2

Answers: 1

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