StackOverflow Questions for Tag: memory-model

getsoubl

Reputation: 1055

C++11 Memory ordering acquire release issue

c++c++11memory-model

Score: 2

Answers: 1

MagicRacoon

Reputation: 3

TSO and store forwarding guarantees

assemblyx86-64cpu-architecturememory-model

Score: 0

Answers: 1

MaPo

Reputation: 855

C++: a question about memory_order_relaxed

c++concurrencystdatomicmemory-model

Score: 3

Answers: 2

Phil

Reputation: 81

Race condition in Morris's algorithm

c++multithreadingmutexsemaphorememory-model

Score: 8

Answers: 1

Lockyer

Reputation: 1401

Do the release-acquire visibility guarantees of std::mutex apply to only the critical section?

c++multithreadingthread-safetymutexmemory-model

Score: 7

Answers: 3

Some Name

Reputation: 9540

Memory ordering of non-atomic object access

cmultithreadingx86stdatomicmemory-model

Score: 2

Answers: 0

glades

Reputation: 4848

How does the memory controller guarantee memory ordering of atomics when propagating cachelines?

c++cpu-architectureatomicstdatomicmemory-model

Score: 3

Answers: 1

Alastair Harrison

Reputation: 1361

What is the effect of the change to the definition of release sequences in the C++20 memory model?

c++concurrencyc++20atomicmemory-model

Score: 5

Answers: 1

Drew Dormann

Reputation: 63947

Is atomic_thread_fence(memory_order_release) different from using memory_order_acq_rel?

c++language-lawyeratomicmemory-barriersmemory-model

Score: 7

Answers: 3

TSK

Reputation: 751

Reorder relaxed atomic operations on the same object

c++atomicmemory-barriersstdatomicmemory-model

Score: 2

Answers: 3

Ivan Kush

Reputation: 3157

What does "release sequence" mean?

c++multithreadingc++11memory-modelstdatomic

Score: 19

Answers: 6

Yriuns

Reputation: 775

Memory Model: What is the difference between `store(x, relaxed); atomic::fence(seq_cst);` and `store(x, seq_cst)`

c++rustmemory-model

Score: 1

Answers: 1

user22425122

Reputation: 17

How to iterate over all possible executions of a program?

c++multithreadingmemory-model

Score: -1

Answers: 2

thb

Reputation: 14464

Can modern x86 hardware not store a single byte to memory?

c++assemblyconcurrencyx86memory-model

Score: 41

Answers: 6

yaoqijun

Reputation: 53

Do atomic operations in Go make sure other variables are visible to other threads?

gomemory-barriersmemory-model

Score: 5

Answers: 2

Oersted

Reputation: 2734

memory ordering on a simple producer/consumer example

c++multithreadingmemory-model

Score: 3

Answers: 1

Oersted

Reputation: 2734

follow up on memory ordering on a simple producer/consumer example

c++multithreadingmemory-model

Score: 0

Answers: 0

Patrick Pan

Reputation: 495

In RISC-V, why setting the `rl` bit on the LR instruction isn't necessary to make the LR/SC sequence sequentially consistent?

riscvmemory-model

Score: 0

Answers: 2

newman

Reputation: 519

How to understand happens-before consistent

javamemory-model

Score: 16

Answers: 5

Alex Guteniev

Reputation: 13719

How C++ Standard prevents deadlock in spinlock mutex with memory_order_acquire and memory_order_release?

c++language-lawyermemory-modelstdatomicspinlock

Score: 8

Answers: 2

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StackOverflow Questions for Tag: memory-model

C++11 Memory ordering acquire release issue

TSO and store forwarding guarantees

C++: a question about memory_order_relaxed

Race condition in Morris&#39;s algorithm

Do the release-acquire visibility guarantees of std::mutex apply to only the critical section?

Memory ordering of non-atomic object access

How does the memory controller guarantee memory ordering of atomics when propagating cachelines?

What is the effect of the change to the definition of release sequences in the C++20 memory model?

Is atomic_thread_fence(memory_order_release) different from using memory_order_acq_rel?

Reorder relaxed atomic operations on the same object

What does &quot;release sequence&quot; mean?

Memory Model: What is the difference between `store(x, relaxed); atomic::fence(seq_cst);` and `store(x, seq_cst)`

How to iterate over all possible executions of a program?

Can modern x86 hardware not store a single byte to memory?

Do atomic operations in Go make sure other variables are visible to other threads?

memory ordering on a simple producer/consumer example

follow up on memory ordering on a simple producer/consumer example

In RISC-V, why setting the `rl` bit on the LR instruction isn&#39;t necessary to make the LR/SC sequence sequentially consistent?

How to understand happens-before consistent

How C++ Standard prevents deadlock in spinlock mutex with memory_order_acquire and memory_order_release?

Race condition in Morris's algorithm

What does "release sequence" mean?

In RISC-V, why setting the `rl` bit on the LR instruction isn't necessary to make the LR/SC sequence sequentially consistent?