CODEWITHSUNDEEP
vhdlcomparatormagnitude
rockstiff
rockstiff

Reputation: 383

4 bit magnitude comparator VHDL

I have to make a 4bit magnitude comparator in VHDL with only concurrent statements (no if/else or case/when).

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Exercise is
port (  A : in std_logic_vector (3 downto 0);
        B : in std_logic_vector (3 downto 0);
        Ag : out std_logic;
        Bg : out std_logic;
        AeqB: out std_logic
       );   
end Exercise;

architecture Comparator of Exercise is

begin
    Ag <= '1'when (A>B) else '0'; 
    Bg <= '1' when (B>A) else '0';  --Problem: Here if i sumulate B="ZZZZ", Bg is 1, asi if B>A 
    AeqB<= '1' when (A=B) else '0'; 
end Comparator;

The problem is that i need to take in count all the other values of std_logic (U,X,Z,W,L,H,-), i know there is the others but cant figure it out how to make the comparator with with/select statement.

Thanks

Upvotes: -1

Views: 11140

Answers (2)

anonymous
anonymous

Reputation: 1

library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity comp_4 is
    port (  A:IN STD_LOGIC_VECTOR(0 to 3);
        B:IN STD_LOGIC_VECTOR(0 to 3);
        ET:OUT STD_LOGIC;
        GT:OUT STD_LOGIC;
        LT:OUT STD_LOGIC);

    end comp_4;

    architecture dataflow of comp_4 is

    begin
    with A-B(0 to 3) select

    ET <=   '1' when "0000",
        '0' when others;

    with A > B select

    GT <=   '1' when true,
        '0' when others;

    with A < B select

    LT <=   '1' when true,
        '0' when others;

    end dataflow;

Upvotes: 0

scary_jeff
scary_jeff

Reputation: 4384

In general you can 'convert' the various values that std_logic can take into either 0 or 1 using the to_01 function. I think it's in package numeric_std.

Upvotes: 0

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