VHDL multiplexer testbench error

Question

I am new to vhdl and trying to make testbench for multiplexer with 5 select lines but it gives me errors (the code is very long so I just copied the part which include the errors )

The code:

    library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all;
    use ieee.numeric_std.all;
    entity Mux_4_to_1_tb is
    end Mux_4_to_1_tb;

    architecture tb of Mux_4_to_1_tb is

    component Mux_4_to_1 is
      port( clock : in std_logic;
        D0, D1, D2, D3 : in std_logic; -- the data lines D0=A0 D1=A1 D2=B0 D3=B1
            S0, S1, S2, S3, S4  : in std_logic; -- the selector switches
            F : out std_logic_vector(2 downto 0)
        );-- the output
    end component;
    constant clockperiod : time := 20 ns;
    signal D0, D1, D2, D3, S0, S1 , S2, S3, S4  , F : std_logic;
    signal selectors : std_logic_vector(4 downto 0);

    begin
    mapping: Mux_4_to_1 port map(D0, D1, D2, D3, S0, S1, S2, S3, S4, F );

    --Concurrent processes
    process
    begin   

      S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '1';wait for clockperiod;
      S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '1'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '0'; S2 <= '0'; S3 <= '1'; S4 <= '1';wait for clockperiod;
      S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '0'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '0'; S4 <= '1';wait for clockperiod;
      S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '1'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '0'; S2 <= '1'; S3 <= '1'; S4 <= '1';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '0'; S4 <= '1';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '1'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '0'; S3 <= '1'; S4 <= '1';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '0'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '0'; S4 <= '1';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '1'; S4 <= '0';wait for clockperiod;
      S0 <= '0'; S1 <= '1'; S2 <= '1'; S3 <= '1'; S4 <= '1';wait for clockperiod;
      S0 <= '1'; S1 <= '0'; S2 <= '0'; S3 <= '0'; S4 <= '0';wait for clockperiod;
      end process;

      process(S4, S3, S2, S1, S0)
      begin
       selectors <= S0&S1&S2&S3&S4;
        end process;

       process
       begin

      --The "assert" keyword allows you to test certain 
      --conditions. In other words, the point of assertion is
      --to allow you to inspect what you expect.

      --Two test cases are presented here. Feel free 
      --to add your own cases.

       --TEST 1
         D0 <= '0';
        D1 <= '1';
        D2 <= '0';
        D3 <= '1';
        wait for clockperiod;
        case selectors is
         when "00000" =>
           assert(F => "000") report "Error 1: 00000" severity error;

Error:

** Error: E:\OneDrive\Engineering\Digital Circuit Design\TestBench.vhd(70): (vcom-1581) No feasible entries for infix operator '='.
** Error: E:\OneDrive\Engineering\Digital Circuit Design\TestBench.vhd(70): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.

The error point me to the line with the assert word.

Also i get this error at the end of the code

code:

 when others =>
     assert true;
  end case;
end process;
end tb;

Error:

** Error: E:\OneDrive\Engineering\Digital Circuit Design\TestBench.vhd(229): VHDL Compiler exiting

The error point me to the last line here.

Answer 1

You're not providing any insight into how this testbench is supposed to operate without revealing the contents of Mux_4_to_1.

There are two things wrong with the assertion statement condition:

assert(F => "000")

F is declared as type std_logic which is not an array type and can't be compared to a string value (which would have an array type determinable by context). Also the relational operator should be >= and not =>, read as 'greater than or equal to'. => is a delimiter used in association.

Changing the relational operator and changing the declaration for F:

signal D0, D1, D2, D3, S0, S1 , S2, S3, S4 :  std_logic; --  , F : std_logic;
signal F:   std_logic_vector (2 downto 0);

generate an error telling us F can't be associated with S4, telling us you have a parameter list error. You don't have enough parameters. It's not an error to not provide an association for outputs which is why it wasn't noticed before, although the reader might assume you changed the declaration of F to get rid of that error a priori.

Adding a signal declaration for a clock:

constant clockperiod : time := 20 ns;
signal clock:   std_logic;

and adding an association:

begin
-- mapping: Mux_4_to_1 port map(D0, D1, D2, D3, S0, S1, S2, S3, S4, F );
mapping: 
    Mux_4_to_1 
        port map (
            clock => clock,
            D0 => D0,
            D1 => D1,
            D2 => D2,
            D3 => D3, 
            S0 => S0,
            S1 => S1,
            S2 => S2,
            S3 => S3,
            S4 => S4, 
            F => F
        );

allows your code to analyze(by concatenating the code found with the others choice to the end of the VHDL code, you don't provide a Minimal, Complete and Verifiable example).

NOTES:

1. clock is not shown driven in the change description and if needed for your tests should be driven by the testbench.
2. Formal association is shown in the port map for the instantation of Mux_4_to_1, it allows you to see missing or wrong formal to actual port associations.
3. Superfluous parentheses surrounding conditions may obscure errors. They are only legal if the expression they contain is legal without them. It can change the error message you see. The lack of a proper relational operator results in a syntax error.