CODEWITHSUNDEEP
verilogfpgahdl
streamliner18
streamliner18

Reputation: 181

Verilog: How to assign the an inout to another inout?

I'm trying to assign the input from an inout port to another inout port used as output. As common practice, I have to set the input port to High-Z:

inout pin5;
inout pin20;
assign pin20 = 1'bz;
assign pin5 = pin20;

This caused both pin5 and pin20 to be routed to high-Z. I know why it's logically happening, but how can I go around it, besides turning pin20 into an input?

Here's the schematics output from my mapper.

Upvotes: 0

Views: 6647

Answers (2)

Greg
Greg

Reputation: 19114

Having two IO pins connected like this isn't common. If it is just for simulations you can connect the pins with the Verilog primitive tran. 

module linked_io ( inout io_A, io_B, input i, c );
  tran link(io_A, io_B);
  assign io_A = c ? i : 1'bz;
endmodule

tran is generally not recognized by synthesizers. Some vendors have a custom macro that is functionally equivalent to tran that specifically work only for there own toolset. You will need to check the user manual or ask your vendor directly if such a macro exists.

Another approach is to selectively alias ports to the same net with the example below. This was added in Verilog-2001 with an example in IEEE1364-2001 § 12.3.3 Port declarations (same example in SystemVerilog's IEEE1800-2012 § 23.2.2.1 Non-ANSI style port declarations).

module linked_io ( .io_A(io), .io_B(io), i, c );
  inout io;
  input i, c;
  assign io = c ? i : 1'bz;
endmodule

This is the only condition I use the Non-ANSI style; ANSI style is much simpler and cleaner. However, I've found limited support with this port aliasing feature. It is a somewhat obscure feature with little demand so it is a low priority for vendors to implement vs high demand features. That said, it may work with your simulator, synthesizer, etc.

Upvotes: 0

Serge
Serge

Reputation: 12354

There is no buffer in your code. But the picture that you show looks like the following to me. The 'test' module gets 2 pins and assigns 'z's. If you leave them hanging, there will stay at this value. In the example below the 'top' module emulates the activity on the pin and assigns 'val' to it. Now the 'pin2' will follow the pattern of 'val' (if enabled) or stay at 'z'. The val actually is the buffer you'd been talking about. 

module top();
   reg val, en;
   wire pin1, pin2;
   // do something with val and en 

   test t(pin1, pin2);
   assign pin2 = en ? 1'bz : val;
endmodule // top

module test(inout pin1, pin2);
   assign pin1 = 1'bz;
   assign pin2 = pin1;
endmodule // test

Upvotes: 0

Related Questions