CODEWITHSUNDEEP
verilogsystem-verilogiverilog
subh
subh

Reputation: 23

What should be the output in the following case?

What should be the o/p in the following case? I have run it on different compilers, got different results in each.

module top;
    reg a,b;
    function int  f(string s);
        $display("%s", s);
        return 1;
    endfunction

    initial begin
        $display(" Experiment 1 ");
        if (  f("hello") & (1==0))  begin
            $display(" 1 : if 1 is true");
        end

        $display(" Experiment 2 ");
        if ( (1==0) & f("hello"))  begin
            $display(" 2 : if 2 is true");
        end
        $display(" Experiment 3 ");
        if (  f("hello") && (1==0))  begin
            $display(" 3 : if 3 is true");
        end
        $display(" Experiment 4 ");
        if ( (1==0) && f("hello"))  begin
            $display(" 4 : if 4 is true");
        end
    end
endmodule

Upvotes: 0

Views: 95

Answers (1)

Serge
Serge

Reputation: 12354

From lrm 11.4.7 Logical operators

The && and || operators shall use short circuit evaluation as follows:

  • The first operand expression shall always be evaluated.
  • For &&, if the first operand value is logically false then the second operand shall not be evaluated.
  • For ||, if the first operand value is logically true then the second operand shall not be evaluated.

According to this, hello should not be printed in '4'. But should be printed in '3'.

cases 1 and 2 can be prone to optimization. I could not find anything in the standard which would prevent the functions from being optimized there. So, i believe that both, insisive and reviera behaved correctly.

Looks like synopsys violates the standard though. My guess is that they over-optimized case '3'.

Upvotes: 1

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