CODEWITHSUNDEEP
verilogsystem-verilog
maskarih
maskarih

Reputation: 867

SystemVerilog changing port type from wire to logic gives error when usingn default_nettype none

I am converting my design from Verilog to SystemVerilog and by default I have 'default_nettype none directive. Here is my design:

`default_nettype none

module my_design 
#(
parameter INPUT_WIDTH  = 16,
parameter OUTPUT_WIDTH = 2*INPUT_WIDTH
)
(
    input  wire signed [INPUT_WIDTH-1 : 0 ]  x_in,
    input  wire signed [INPUT_WIDTH-1 : 0 ]  y_in,
    output wire signed [OUTPUT_WIDTH-1 : 0]  z_out
);

Which compiles whithout any issue. However, when I change wire to logic as follow:

module my_design 
#(
parameter INPUT_WIDTH  = 16,
parameter OUTPUT_WIDTH = 2*INPUT_WIDTH
)
(
    input  logic signed [INPUT_WIDTH-1 : 0 ]  x_in,
    input  logic signed [INPUT_WIDTH-1 : 0 ]  y_in,
    output logic signed [OUTPUT_WIDTH-1 : 0]  z_out
);

I am getting the following error for all my port signals:

ERROR: [VRFC 10-1103] net type must be explicitly specified for 'x_in' 
when default_nettype is none

Which is very strange to me since I have explicitly decalred all the ports. I am using Vivado Simulator 2018.2. I am using the following command to compile the above codes:

xvlog --sv -f files.f

And files.f contains my design and test file only.

Upvotes: 0

Views: 6321

Answers (1)

dave_59
dave_59

Reputation: 42698

Input ports are implicitly wire net types with an implicit logic data type. SystemVerilog chose these defaults to be backward compatible with Verilog.

So your original Verilog input declaration was an explicit wire with an implicit logic data type. You changed it to an implicit wire nettype with an explicit logic data type. But the result is functionally the same. You need to add back the wire keyword.

The following are all functionally equivalent:

 input signed [INPUT_WIDTH-1 : 0 ]  x_in, // implicit wire logic
 input logic signed [INPUT_WIDTH-1 : 0 ]  x_in, // implicit wire
 input wire signed [INPUT_WIDTH-1 : 0 ]  x_in, // implicit logic
 input wire logic signed [INPUT_WIDTH-1 : 0 ]  x_in, // explicit

Upvotes: 4

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