CODEWITHSUNDEEP
verilogfpgaxilinx
vu2swz
vu2swz

Reputation: 145

32-bit adder subtractor model compile error: Illegal Lvalue

I am designing a 32 adder/subtractor using the following specification.

Inputs are connected to FFs with synchronous reset and an enable signal. The output from these registers are connected to the add/subtract. The output from the add/subtract goes to another set of FFs whose output is connected to the output port. Now when the inputs are given to the module, outputs are generated after 2 clock cycles.

Here is my design.


    module adder(A,B,Add_Sub,Out);
      input [31:0]A;
      input [31:0]B;
      input Add_Sub;
      output [32:0]Out;
      reg [32:0]Out;
      always @( A or B or Add_Sub)
        begin
          if(Add_Sub == 1)
            Out = A + B;
          else
            Out = A -B;
        end
    endmodule
    
    module DFF(D,clk,reset,enable, Q);
      input[31:0] D; // Data input
      input clk,reset,enable;
      output[31:0] Q; // output Q
      reg[31:0] Q;
    always @(posedge clk or posedge reset)
    begin
        if(reset)
            Q <= 32'b0;
        else if (enable)
            Q <= D;
    end
    endmodule
      
    module register_adder(A,B,CLK,RST,ADD_SUB,EN,OUT,OUT_READY);
      input [31:0]A,B;
      input CLK,RST,ADD_SUB,EN;
      output [32:0]OUT;
      reg [32:0]OUT;
      wire [31:0]Q1,Q2;
      wire[32:0]Q3;
      output OUT_READY;
      always @(posedge CLK or A or B or ADD_SUB)
        begin
          DFF F1(A,CLK,RST,EN,Q1);
          DFF F2(B,CLK,RST,EN,Q2);
          adder A1(Q1,Q2,ADD_SUB,Q3);
          DFF F3(Q3,CLK,RST,EN,OUT);
          OUT_READY <=1'b1;
        end
    endmodule

While compiling the model, I'm getting the following errors.

Compiling source file : q6.v

    q6.v: L42: error: Illegal Lvalue
    q6.v: L42: error: syntax error, unexpected IDENTIFIER, expecting LE or '='
    q6.v: L43: error: Illegal Lvalue
    q6.v: L43: error: syntax error, unexpected IDENTIFIER, expecting LE or '='
    q6.v: L44: error: Illegal Lvalue
    q6.v: L44: error: syntax error, unexpected IDENTIFIER, expecting LE or '='
    q6.v: L45: error: Illegal Lvalue
    q6.v: L45: error: syntax error, unexpected IDENTIFIER, expecting LE or '='
    8 errors in compilation

I cannot find the issue on analysis.

Upvotes: 0

Views: 242

Answers (1)

toolic
toolic

Reputation: 62236

Your module instances should not be inside an always block.

OUT_READY should not be inside the always either, and it should use the assign keyword and the blocking assignment operator (=).

I no longer get compile errors with the following code:

module register_adder(A,B,CLK,RST,ADD_SUB,EN,OUT,OUT_READY);
  input [31:0]A,B;
  input CLK,RST,ADD_SUB,EN;
  output [32:0]OUT;
  reg [32:0]OUT;
  wire [31:0]Q1,Q2;
  wire[32:0]Q3;
  output OUT_READY;

  DFF F1(A,CLK,RST,EN,Q1);
  DFF F2(B,CLK,RST,EN,Q2);
  adder A1(Q1,Q2,ADD_SUB,Q3);
  DFF F3(Q3,CLK,RST,EN,OUT);

  assign OUT_READY = 1'b1;
endmodule

Here is the fixed code on edaplayground (you need to create an account if you don't already have one -- it's free).

The code generates warning messages on some simulators. For example, with Cadence I see:

      DFF F3(Q3,CLK,RST,EN,OUT);
              |
xmelab: *W,CUVMPW (./testbench.sv,42|14): port sizes differ in port connection(33/32) for the instance(register_adder) .

You need to decide if you really want 32 or 33 bits.

Upvotes: 1

Related Questions