CODEWITHSUNDEEP
verilogsystem-verilogtest-bench
priscilla
priscilla

Reputation: 11

Why am I getting the error : part select cannot be applied to scalar in my testbench?

I have designed a multiplier circuit that has two 32-b inputs, that would be split into two 16-b values and multiplied separately after which the results will be added together. Here is a part of the logic:

   parameter WordLen1 = 32, WordLen2 = 16; 
   output [WordLen2-1:0] M;
   input clk; 
   input signed [WordLen1-1:0] X, W1;

   reg signed [WordLen1-1 :0] X_reg, W1_reg, M;
   wire signed [WordLen2-1:0] mul1, mul2, M_out;

   assign mul1 = X_reg[31:16] * W1_reg[31:16];
   assign mul2 = X_reg[15:0] * W1_reg[15:0];
   assign M_out = mul1 + mul2;

The test bench of the code is as follows:

 module testbench;

reg clk;
parameter WL1 = 32, WL2 = 16;
reg [WL1-1:0] Xinarray [0:1];           // define memory arrays to hold inputs
reg [WL1-1:0] W1inarray [0:1]; 

wire [WL2-1:0] M;
integer i; 

mult_hidden uut(M,clk,X,W1);

initial begin  
$readmemb("input.txt", Xinarray);      // read values into arrays from files 
$readmemb("weight1.txt", W1inarray);  
    
 
 $display("Starting...");
 for (i=0; i<=1; i=i+1) // loop through all values in the memories  
 begin   
 X[31:0] = Xinarray[i]; // set the inputs from the memory arrays  
 W1[31:0] = W1inarray[i];  
  
 $display("...Done");  
 $finish; 
 end  
 end 
 
 always #1 clk = !clk;
 endmodule

The input files have 32-b binary numbers each. On compiling the code, I am getting the following error messages :

 X[31:0] = Xinarray[i]; // set the inputs from the memory arrays
 |
ncvlog: *E,WANOTL (../src/mult_hidden_tb.v,21|1): A net is not a legal lvalue in this context [9.3.1(IEEE)].
 X[31:0] = Xinarray[i]; // set the inputs from the memory arrays
 |
ncvlog: *E,NOPSOS (../src/mult_hidden_tb.v,21|1): Part-select operator cannot be applied to scalar [4.2.1(IEEE)].
 W1[31:0] = W1inarray[i];
  |
ncvlog: *E,WANOTL (../src/mult_hidden_tb.v,22|2): A net is not a legal lvalue in this context [9.3.1(IEEE)].
 W1[31:0] = W1inarray[i];
  |
ncvlog: *E,NOPSOS (../src/mult_hidden_tb.v,22|2): Part-select operator cannot be applied to scalar [4.2.1(IEEE)].
make: *** [mult_hidden] Error 1

How do I need to modify my testbench so that the input text files are read and the 32-b inputs are split into 16-b values each for the multiplication to happen?

Upvotes: 1

Views: 3529

Answers (2)

toolic
toolic

Reputation: 62236

You need to explicitly declare the signals in the testbench.

Verilog implicitly declares X as a 1-bit net (like a wire). But, you need it to be a different type and bit width. The same is true for W1. Adding this line to your testbench clears up all the compile error messages:

   logic signed [WL1-1:0] X, W1;

Unlike wire, logic allows the procedural assignments (in the initial block).

Place this line at the top of your testbench. For example:

module testbench;

reg clk;
parameter WL1 = 32, WL2 = 16;
reg [WL1-1:0] Xinarray [0:1];           // define memory arrays to hold inputs
reg [WL1-1:0] W1inarray [0:1];
logic signed [WL1-1:0] X, W1;     // <------- Here

Upvotes: 0

vitalstatistix
vitalstatistix

Reputation: 340

There are a couple problems right off the bat:

  1. In your module, you're not assigning your input X and W1 to the X_reg and W1_reg registers.
  2. You haven't declared your X and W1 variables in your testbench. They're inferred as 1 bit wires which can't be assigned like you're trying to do.
  3. This is stylistic but your variable names obscure meaning. Consider renaming them to make understanding your code easier both for yourself and others.

Upvotes: -1

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