CODEWITHSUNDEEP
verilogsystem-verilogtest-bench
Sharathraj M
Sharathraj M

Reputation: 29

How to use the output of task1 in another task2?

I want to use the output from task calc(ton,toff) into task clk_gen, but the output from clk_gen is ton = 0 , toff = 0.

Question 1: why it is not ton = 24 ,ton =16
Question 2: why it is not ton = x  ,ton = x
Question 3: why it is  ton = 0 ,toff = 0

having clk period of clk as 40 ns having clk period of clk2 as 10 ns

`timescale 1ns / 1ps
module newm();
reg clk=0;
real  period = 40;
reg clk2 =0;
always #5 clk2 = ~ clk2;

calculating ton and toff from task : calc

task calc(input real dutycycle,input real period,output real ton,output real toff);
ton = dutycycle * period;
toff = (1-dutycycle) * period ;
$monitor("values inside calc,  ton = %0d ,toff = %0d",ton,toff);// output :values inside calc ,ton = 24,toff = 16
endtask

using ton and toff at clk_gen

task clk_gen(input real ton,input real toff);
$monitor("values inside clk_gen ,ton = %0b ,toff = %0b",ton,toff);   // ----- why ? output:values inside clk_gen ,ton = 0,toff = 0 
@(posedge clk2);
forever begin
clk =1;
#ton;
clk= 0;
#toff;
end
endtask

running the code

reg ton;
reg toff;  
  
initial begin
calc(0.6,period,ton,toff);
clk_gen(ton,toff);
end 
initial begin
#200;
$finish();
end
endmodule

Upvotes: 0

Views: 123

Answers (1)

toolic
toolic

Reputation: 62037

In module newm, you declared ton and toff as 1-bit variables, but you should have declared them as type real. Verilog converts 24 to 0, which is why you see 0 inside the calc_gen task.

Change:

reg ton;
reg toff;

to:

real ton;
real toff;

Upvotes: 1

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