CODEWITHSUNDEEP
vhdlfpgavivadointel-fpgaflip-flop
Marcu Petric
Marcu Petric

Reputation: 1

CLOCK_DEDICATED_ROUTE error in creating an RS latch

I am trying to describe a RS asynchronous latch in VHDL. I receive this error from vivado.

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets S_IBUF] >

S_IBUF_inst (IBUF.O) is locked to IOB_X0Y93 and S_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y7

The code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RSlatch is
Port ( 
R, S : in std_logic;
Q: out std_logic
 );
end RSlatch;

architecture Behavioral of RSlatch is

begin
 process (R, S)
 variable aux : std_logic := '0';
 begin
  if (R = '1') then 
  aux := '0';
  elsif(S = '1') then  
  aux := '1';
  else
  aux := aux;
  q <= aux;
  end if;
  end process;
 end Behavioral;

I am not using a clock so I do not understand why do I receive this error.

Upvotes: 0

Views: 427

Answers (2)

Justin N
Justin N

Reputation: 911

You haven't posted enough information to know for sure what's wrong. But your S input likely isn't on a proper clock pin. Since this doesn't appear to be a full-scale design you're probably fine setting the property in the warning message.

Note that while you may not be explicitly using a clock in your code, Vivado has chosen to use clocking resources to implement it.

Upvotes: 0

Matthias Schweikart
Matthias Schweikart

Reputation: 697

You are getting a clock signal, because your code successfully describes a latch which is built in as a single predefined cell. Its clock input is connected to a signal combined from R and S (also its D-input signal is combined from R and S). It is not recommended to use latches, as they are difficult to handle for timing closure, especially when R and S are both kind of clock signal.

Upvotes: 1

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