CODEWITHSUNDEEP
verilogfpgavivadosynthesissynplify
Xiuhua Yang
Xiuhua Yang

Reputation: 27

How to use the command "+incdir+" in synplify script(.tcl) when one verilog file include another verilog file?

I insert a verilog file into another verilog file by using "`include " And when I used the synplify script(*.tcl) to try to synthesize, one error occured:

invalid command name "+incdir+<...>"

It seems like I have to use the command "+incdir+" according to online documents, but what something wrong happened?

Example page 365

If your project has Verilog files with `include statements, you must use
the +incdir+ <file name> argument when you specify the vlogan
command. You enter the +incdir+ in the Verilog Compile field in the VCS
Options dialog box, as shown below:

Upvotes: -2

Views: 704

Answers (1)

Mustafa Hakan Solmaz
Mustafa Hakan Solmaz

Reputation: 1

quoting from the documentation : if you have an include file,

`include "component.v"
module Top (input a, output x);
...
endmodule

you need to tell the relative directory of the include file (component.v) with respect to the directory of synplify script(.tcl) :

vlogan -work work Top.v +incdir+ ./ +incdir+ ../include_dir1

etc.

Upvotes: -1

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