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verilogfpga
Erasmus
Erasmus

Reputation: 427

Parse error when I try to use Verilog; testbenching an LFSR doesn't work

I am currently working on random number generation using Verilog. Sources have indicated that using Linear Feedback Shift Registers are one of the best ways to randomize MSBs. So I decided to code and testbench an LFSR. Snippet is below:

module lfsr_counter(clk, reset, ce, lfsr_done);

input clk, reset, ce;
output lfsr_done;

reg lfsr_done;
reg [10:0] lfsr;
initial lfsr_done = 0;
wire d0,lfsr_equal;

xnor(d0,lfsr[10],lfsr[8]);
assign lfsr_equal = (lfsr == 11'h359);

always @(posedge clk,posedge reset) begin
    if(reset) begin
        lfsr <= 0;
        lfsr_done <= 0;
    end
    else begin
        if(ce)
          lfsr <= lfsr_equal ? 11'h0 : {lfsr[9:0],d0};
          lfsr_done <= lfsr_equal;
    end
end
endmodule


module testbench();

reg clk, reset, ce;
wire lfsr_done;

lfsr_counter dut(clk, reset, ce, lfsr_done); // Design Under Test

initial
begin

    reset = 0;
        clk = 1;
    ce = 0;

        #100
    ce = 1;
        #200 $finish;
end

//Generate Clock
always #10 clk = !clk; 

endmodule

But I keep getting these parse errors:

enter image description here

I don't really get it. I'm using Verilogger Pro btw

Upvotes: 1

Views: 1578

Answers (1)

Tim
Tim

Reputation: 35923

I think always block terms are separated by or, not a comma.

always @(posedge clk or posedge reset) begin

Upvotes: 1

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