CODEWITHSUNDEEP
vhdlhdlmodelsim
crete
crete

Reputation: 1

VHDL concurrent assertions and delta cycles

I am trying to use VHDL concurrent assertions in order to verify that a signal correctly drives another. As they should be directly connected at some times (no latching), I want to use a concurrent assertion of the following form :

assert (driver_sig = driven_sig) or not check_sigs report "Error" severity error;

Here, check_sigs simply serves as a flag that masks the assertion when the signals are not connected.

However, this does not work in this form, because it takes some amount of delta cycles to update the driven signal (about 10), and the assertion triggers an error in these delta cycles.

There was a solution given in this post in which we add 'delayed(0 ns) to the driver signal in order to take the value after a delta cycle. However, this only works if the number of delta cycles between the signals is only one, so I still have the problem, just one delta cycle later (when viewing from time deltas mode in modelsim).

Is there a way to adapt this solution for any amount of delta cycles ? Which means we would delay the checked signals until the last delta cycle of a timestep, instead of checking at every delta. (or, once per timestep, beginning or end)

Upvotes: 0

Views: 129

Answers (1)

Tricky
Tricky

Reputation: 4471

A one liner in VHDL actually infers a process that is sensitive to all signals in that one liner. So why not simply wrap the assertion in a process that is only sensitive to the later signal? Assuming that driven_sig is the one you want to check, use:

process(driven_sig, check_sigs)
begin
  assert (driver_sig = driven_sig) or not check_sigs report "Error" severity error;
end process;

this way it only performs the assertion when driven_sig or check_sigs changes, but not the driver_sig.

Upvotes: 0

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