CODEWITHSUNDEEP
syntaxverilog
Sammyr93
Sammyr93

Reputation: 45

Recieving the following error: "line 36 expecting 'endmodule', found 'if'

On the line with if(lr == 0) I am recieving the following error "expecting 'endmodule', found 'if'. The Verilog code is of a 8-bit shift register that functions as a left and right shifter and can choose between arithmetic and logical shifting. I can't see why I am receiving the error. It may be a some type of syntax error since I am new to Verilog. Thanks for any help in advance.

module shifter(
input [7:0] shift_in,
input [2:0] shift_by,

 // 0 for left, 1 for right
input lr,

 //0 for logical, 1 for arithmetic
input arith,
output reg signed [7:0] shift_out
);

//left shift
if(lr == 0) 
begin
    assign shift_out = shift_in << shift_by;
    assign shift_out[0] = 1'b0;
end
//right shift
else begin
    //logical shift
    if (arith == 0) begin
        assign shift_out = shift_in << shift_by;
        assign shift_out[7] = 1'b0;
    //arithmetic shift
    end else begin
        assign shift_out[7] = shift_in[7];
        assign shift_out = shift_in << shift_by;
    end
end

endmodule

Upvotes: 0

Views: 5395

Answers (1)

Morgan
Morgan

Reputation: 20554

You can not use if statments like that with assign. Place in an always block and remove the assign.

always @* begin
//left shift
if(lr == 1'b0) 
begin
    shift_out = shift_in << shift_by;
    shift_out[0] = 1'b0;
end
//right shift
else begin
    //logical shift
    if (arith == 0) begin
        shift_out = shift_in << shift_by;
        shift_out[7] = 1'b0;
    //arithmetic shift
    end else begin
        shift_out[7] = shift_in[7];
        shift_out = shift_in << shift_by;
    end
end
end

Upvotes: 4

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