CODEWITHSUNDEEP
verilogfpgasystem-verilog
Rohit Dilip
Rohit Dilip

Reputation: 11

Running into errors while trying to move signal to external module

I have two modules namely main.v and signal.v.

In main.v, I have a few lines of code that update 16 bit reg tx with a value corresponding to a square wave. 

   reg [1:0] counter;
   reg [15:0] tx;
   always @(posedge clk) begin
      counter = counter + 1;
      if (counter[1] == 1) begin
        tx[15:0] <= 16'b1010101010101010;
      else
        tx[15:0] <= 16'b0000000000000000;
   end

This works fine. Eventually, though, I want to move this signal over to another file signal.v, because the signal that I pass to tx will grow steadily more complicated. I ran into errors when I try to do this. Initially, I tried to move all the above code to the file signal.v. Then used a wire between the two files as shown.

module signal(clk, get_tx);
   input clk;
   output reg get_tx;
   reg [1:0] counter;

   always @(posedge clk) begin
      counter = counter + 1;
      if (counter[1] == 1) begin
        get_tx[15:0] <= 16'b1010101010101010;
      else
        get_tx[15:0] <= 16'b0000000000000000;
   end

Then in main.v, I tried to add

wire get_tx;
reg [15:0] tx;
signal my_signal(.clk(clk), .get_tx(get_tx));
always @( get_tx ) begin
     tx <= get_tx;
end

Based on what I see in the output oscilloscope, this method isn't working, and I'm not certain why this is. The first case seems to work fine, so I don't know why it is failing when I move to the second case (the signals just look completely different). I would appreciate any help/advice!

Upvotes: 0

Views: 76

Answers (1)

Roman
Roman

Reputation: 385

First of all will be better to understand your connections and simulate your code if you add full code with modules declarations.
The problems are in the signal types. Try to change output to wire. As well you need to declare bus, not just 1 bit signal. And give an initial value to your counter (in other case it will do follow operation 'X' +1 which gives 'X' in result and your condition if (counter[1] == 1) will never be achieved).

module signal(clk, get_tx);
   input clk;
   output [15:0] get_tx;
   reg [15:0] tx_out;
   reg [1:0] counter = 2'd0;

   always @(posedge clk) begin
      counter = counter + 1;
      if (counter[1] == 1)
        tx_out[15:0] <= 16'b1010101010101010;
      else
        tx_out[15:0] <= 16'b0000000000000000;
   end
   assign get_tx = tx_out;
endmodule

Next error in upper module, there you also need to declare bus rather than just one bit wire [15:0] get_tx;.
Try to fix this errors and your modules will work.

Upvotes: 2

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