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componentsvhdlfpgaactive-hdl
Amir133
Amir133

Reputation: 2722

Can not use component in active -hdl 10

I use active-hdl 10 for compile and simulation a DFlipFlop structural. my code compiled successfully without any error or warning but when I simulate it, my output have unknown value .(see picture)

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I compile and simulate this code in xilinx and active-hdl 8 without any problem.

D_FlipFlop code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_FlipFlop is
Port ( D : in  STD_LOGIC;
       Clk : in  STD_LOGIC;
       Q : inout  STD_LOGIC);
end D_FlipFlop;

architecture Behavioral of D_FlipFlop is
component DLach Port ( D : in  STD_LOGIC;
                          C : in  STD_LOGIC;
                          Q : inout  STD_LOGIC;
                          Qprim : inout  STD_LOGIC);                            

end component;                                                
Signal Y : STd_logic;
Signal Clk_Not : Std_Logic;
Signal out1 : Std_Logic;
Signal out2 : Std_Logic;
begin
Clk_Not<=not(clk);
h1 : DLach port map(D=>D,C=>clk,Q=>Y,Qprim=>out1);
h2 : DLach port map(Y,Clk_Not,Q,out2);
end Behavioral;

Dlach code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DLach is
Port ( D : in  STD_LOGIC;
       C : in  STD_LOGIC;
       Q : inout  STD_LOGIC:= '0';
       Qprim : inout  STD_LOGIC:= '1');
end DLach;

architecture Behavioral of DLach is

Signal first : Std_logic ;
Signal second : Std_logic ;
Signal D_not : Std_logic ;

begin      

D_Not <= not(D);

first <= D Nand C;
second <= D_not nand C;

Q <= first nand Qprim;
Qprim <= second nand Q ;

end Behavioral;

I research a lot but I cant find the answer. so I think this dosent work for who they use trial version of active -hdl.

Upvotes: 0

Views: 471

Answers (1)

Amir133
Amir133

Reputation: 2722

I search a lot about this problem, it seems no one appear with this problem. so I think this problem occured on trial version of active -hdl 10 or cracked versions.

Upvotes: 0

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