CODEWITHSUNDEEP
fpgaspinalhdl
natanvotre
natanvotre

Reputation: 111

How can I make a ternary condition in SpinalHDL?

I would like to make a ternary condition in SpinalHDL as a ternary assignment in Verilog:

e.g.

wire my_condition = (this == that);

wire [1:0] my_ternary_wire = my_condition ? 2'b10 : 2'b01;

desired SpinalHDL code:

val myCondition = this === that

val myTernaryWire = myCondition ? B(3) : B(1)

Upvotes: 2

Views: 142

Answers (1)

natanvotre
natanvotre

Reputation: 111

I just saw it is possible to use:

val myCondition = this === that

val myTernaryWire = myCondition ? B(3) | B(1)

just changing : to |

Upvotes: 2

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