StackOverflow Questions for Tag: memory-model

Abhishek

Reputation: 11

Relaxed Memory Model for Interpreted Languages

compiler-optimizationinterpretermemory-model

Score: -1

Answers: 1

Davy Landman

Reputation: 15438

How to reduce the (writer side) performance penalty for sharing a small structure between two threads?

c++lockingmemory-barriersthread-synchronizationmemory-model

Score: 1

Answers: 0

Davy Landman

Reputation: 15438

Do you need to pair memory_order_acquire and memory_order_release around a block of code?

c++memory-barriersstdatomicmemory-model

Score: 0

Answers: 0

Har

Reputation: 23

Why no data races in sequentially consistent executions is enough to guarantee that there will be no data races in all executions?

javamemory-modeljava-memory-modeljls

Score: 2

Answers: 1

Alekseev Artem

Reputation: 85

[C++ Memory model]: How to guarantee that read operation would not be reordered after another read

c++multithreadingmemory-model

Score: 8

Answers: 0

Daniel Langr

Reputation: 23527

Does STLR(B) provide sequential consistency on ARM64?

c++x86-64atomicarm64memory-model

Score: 8

Answers: 1

Zazaeil

Reputation: 4119

How come `gcc` did not emit any `fence` instuction? Ain't memory barriers needed here?

cassemblyx86atomicmemory-model

Score: 0

Answers: 0

x f

Reputation: 93

C++ fetch_xx function memory order

c++concurrencymemory-model

Score: 0

Answers: 1

absuu

Reputation: 377

C++ Memory Model - Sequentially Consistent

c++multithreadingparallel-processingatomicmemory-model

Score: 0

Answers: 0

akreuzkamp

Reputation: 31

Cache coherence for a data race free programs

multiprocessingcpu-cachethread-synchronizationmemory-model

Score: 0

Answers: 1

ov3rdr1v337

Reputation: 79

RMW oprimisation in the Sequential consistency

multithreadingarchitecturesequentialmemory-model

Score: 1

Answers: 1

TwITe

Reputation: 440

How happens-before covers single variable write and read?

javacpu-cachememory-modeljava-memory-model

Score: 1

Answers: 1

Arjun

Reputation: 3803

Counterintuitive memory allocation

memoryrustmemory-model

Score: 0

Answers: 1

codesavesworld

Reputation: 793

C++ sequential consistency and happens before relation

c++multithreadingatomicstdatomicmemory-model

Score: 1

Answers: 1

codesavesworld

Reputation: 793

Why can relaxed operation be reordered? Doesn't program order imply happens-before?

c++atomicmemory-barriersstdatomicmemory-model

Score: 1

Answers: 1

Pluto

Reputation: 1062

How to understand the changes to sequentially-consistent ordering in C++20?

c++multithreadingc++20memory-model

Score: 3

Answers: 1

TwITe

Reputation: 440

Multicopy atomicity vs Cache Coherence

cachingatomiccpu-architecturecpu-cachememory-model

Score: 1

Answers: 1

Anton3

Reputation: 586

What are the optimal std::memory_orders for this scenario of a coroutine waiting on an event?

c++atomicmemory-barriersmemory-modelrelaxed-atomics

Score: 5

Answers: 0

Sourav Kannantha B

Reputation: 3299

Does C++ provide a complete set of memory barriers?

c++multithreadingcomputer-sciencememory-barriersmemory-model

Score: 0

Answers: 0

Mona the Monad

Reputation: 2455

AArch64 memory synchronization operations on multiply-mapped addresses

cachingarm64memory-barriersmemory-modelvirtual-address-space

Score: 1

Answers: 1

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StackOverflow Questions for Tag: memory-model

Relaxed Memory Model for Interpreted Languages

How to reduce the (writer side) performance penalty for sharing a small structure between two threads?

Do you need to pair memory_order_acquire and memory_order_release around a block of code?

Why no data races in sequentially consistent executions is enough to guarantee that there will be no data races in all executions?

[C++ Memory model]: How to guarantee that read operation would not be reordered after another read

Does STLR(B) provide sequential consistency on ARM64?

How come `gcc` did not emit any `fence` instuction? Ain&#39;t memory barriers needed here?

C++ fetch_xx function memory order

C++ Memory Model - Sequentially Consistent

Cache coherence for a data race free programs

RMW oprimisation in the Sequential consistency

How happens-before covers single variable write and read?

Counterintuitive memory allocation

C++ sequential consistency and happens before relation

Why can relaxed operation be reordered? Doesn&#39;t program order imply happens-before?

How to understand the changes to sequentially-consistent ordering in C++20?

Multicopy atomicity vs Cache Coherence

What are the optimal std::memory_orders for this scenario of a coroutine waiting on an event?

Does C++ provide a complete set of memory barriers?

AArch64 memory synchronization operations on multiply-mapped addresses

How come `gcc` did not emit any `fence` instuction? Ain't memory barriers needed here?

Why can relaxed operation be reordered? Doesn't program order imply happens-before?