CODEWITHSUNDEEP
verilogfpga
Bruno
Bruno

Reputation: 458

What is the difference between these verilog codes?

I'm was following a tutorial to blink a led in my fpga. These are the codes presented :

1) 

module LED (    
    input      [17:0] SW,
    output reg [17:0] LEDR
);    
    assign led = switch;
endmodule

2) --------

module LED (    
    input [17:0] SW,
    output reg [17:0] LEDR
);
    always @(*)
        led = switch;
endmodule

3) ---------

module LED (        
    input CLOCK_50,
    input [17:0] SW,
    output reg [17:0] LEDR
);

    always @(posedge CLOCK_50)
        LEDR = SW;
endmodule

Upvotes: 0

Views: 593

Answers (1)

jwp36
jwp36

Reputation: 146

Your first example uses continuous assignment to set the value of led to the value of switch. It's like connecting led and switch directly with a wire. Whenever switch changes, led also changes.

Your second example does the same thing but uses an always block. always blocks have a sensitivity list, which contains signals that will trigger the block to run. In this case, it's *, meaning that it triggers any time any of the signals in the blocks change. I believe this is identical to your first example.

Your third example uses sequential logic to set LEDR to SW. In this case, the always block triggers only when the CLOCK_50 signal goes high from a non-high state. If CLOCK_50 never rises, LEDR is never set to any value.

By the way, I don't think your first or second examples are synthesizable. I think led and switch should be LEDR and SW.

These articles give a better description of the concepts in your examples:

Assignments : http://verilog.renerta.com/mobile/source/vrg00005.htm

Always Blocks: http://www.asic-world.com/verilog/verilog_one_day3.html

Upvotes: 1

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